Live Webcast: Meeting the Challenges of DDRx Design
DDR2 and DDR3 (Double Data Rate) have become the dominant memory standards for high-bandwidth applications, yet developing proper routing constraints and meeting set-up and hold times can be a challenge.
In this webcast, we’ll cover some of the basic electrical requirements of DDR2/DDR3 interfaces, show you how to meet the timing and signal integrity (SI) requirements of these memory interfaces, and provide tips on developing these memory subsystems.
Included will be a HyperLynx demonstration that shows how quickly and easily you can analyze DDRx interfaces for SI and timing issues.
What You Will Learn
- The differences between the DDRx standards
- Electrical requirements of DDR2 and DDR3
- How to develop a DDR memory subsystem
- How to use HyperLynx to validate your DDRx system timing
Who Should Attend
- Engineers and Managers designing high-speed memory systems
- Hardware Engineers, Signal Integrity Engineers, and PCB Designers, regardless of EDA tools currently used
- Current HyperLynx customers interested in DDRx applications (call for special DDRx upgrade pricing!)
- What: Meeting the Challenges of DDRx Design
- When: Thursday 4th of March 2010
- Where: Online
- Time: 16:00 PM CET
- Duration: 1 hour
- Registration: Web