Live Webcast: Introducing ModelSim DE
Support for Xilinx SecureIP and Assertion-Based Verification with SystemVerilog and PSL
10th of February 2011
You already know that ModelSim is the simulator of choice for leading electronics companies in all industries. In addtion to native compile, single kernel simulation technology, an intuitive, easy-to-use GUI, integrated project management, source code templates and wizards, we now offer support for Xilinx SecureIP and assertion-based verification with SystemVerilog and PSL support. The web seminar will review the new features and capabilities now available.
Who Should Attend
- Design and Verification engineers
What you will learn
- How the new Modelsim DE will help you to bring your verification to a higher advanced level
- Basic understanding of assertions
- How assertions can help to get functional coverage of your design
About the Presenter Walter Gude
Walter has 19 years experience in ASIC/FPGA design and holds a MS in Electrical Engineering from Washington University in St. Louis. He worked for 6 years doing ASIC design at Tellabs Operations. From there, he went to work for Mentor Consulting where he consulted on various projects including time spent in Munich Germany and Helsinki Finland. For the last 5 years Walter has worked as an Application Engineer supporting Mentor's line of Functional Verification Projects.
Live Webinar: Increase PCB Design Productivity with the PADS ES Suite from Mentor Graphics. You’ll Learn how to use the Analysis and Simulation Capabilities in the PADS ES Suite so You can get Your PCB Design Right the First Time.Live Webcast: Manage PCB Trace Lengths for Optimal System Timing
Live Webinar: Learn how to Determine the Best Trace Lengths for PCB Routing and how to Determine Allowable Trade-Offs to Meet System Timing Goals Using Signal Integrity Simulation.