Practical Insights for Smarter Enginering; technical Workshop with Inventas, Siemens and InnoFour

 

Welcome to a day at Inventas Oslo, tailored for FPGA-developers. Together with Inventas and Siemens EDA, we invite you to a free, practical session where theory meets real-world application. Bring your laptop and your own code, and gain hands-on experience with advanced verification techniques. We wrap up the day with an afterwork, where conversations can continue in a more relaxed setting.

 

FPGA verification with advanced debugging, simulation flows and modern test-bench methodologies

Through these sessions with presentations and a hands-on workshop, we will focus on practical application, giving you tools and techniques you can take directly into your own projects. This afternoon is also a great opportunity to exchange experiences with others working in FPGA-development across industries.

 

You will learn:

• Efficient simulation flows using the Questa environment
• How to structure and streamline build-and-run processes
• Advanced debugging techniques using Visualizer
• Performance analysis and bottleneck identification
• Coverage analysis and verification closure
• Practical approaches to structured testbench development using UVVM
• How to automate regression testing workflows

 

About the sessions

 

• Hands-on workshop:

Advanced hands-on workshop: Anticipating Bugs Before Simulation – Early RTL Issue Detection in Practice; by Faïçal Chtourou - DVT Field Application Engineer at Siemens EDA

Building on the previous hands-on workshop, this advanced session moves earlier in the verification flow: from debugging failures to preventing them. Participants will work through practical labs focused on identifying RTL design risks before they reach simulation, including coding-quality issues, structural problems, connectivity mistakes, clock and reset concerns, and implementation-intent mismatches. The goal is to help teams improve RTL readiness, shorten debug cycles, and make design reviews more systematic and effective.

 

Participants should bring their own laptops; all required tools and lab environments will be provided onsite.

 

• Presentation:

Advanced Randomization with UVVM – Smarter Stimulus for VHDL Verification; by Marius Elvegård, Senior FPGA Developer & Discipline leader Digital at Inventas.

 

This session focuses on advanced randomization concepts in UVVM and how structured random stimulus can improve verification quality in VHDL-based environments. We will present practical techniques for controlling value ranges, applying exclusions and weighting, improving corner-case coverage, and keeping test intent readable and maintainable.

 

• Presentation: 

Agentic AI in Questa One – A New Approach to Verification Productivity; by Faïçal Chtourou.

 

Questa One is a major release for AI-powered, data-driven verification with agentic AI capabilities enabling smarter, goal-driven workflows.

 

This session introduces the Questa One Agentic Toolkit and explores how agentic AI can support tasks such as RTL creation, verification planning, analysis, debug, and closure. Siemens AI-driven workflows can leverage design context, results, logs, waveforms, assertions, and verification intent to assist engineers throughout verification while maintaining human oversight through review and approval steps. 

 

 

• Guest lecture:

Building a RISC-V processor from scratch Yngve Hafting; Lecturer at the Research Group for Robotics and Intelligent Systems at Oslo University

 

Yngve Hafting from the Department of Informatics at the University of Oslo (UiO) has developed a small RISC-V processor from scratch in VHDL, with a focus on simple and readable RTL. In this presentation, he will take us through the implementation and some of the design choices behind it. He will also explore how full control of the RTL opens up for optimization, custom instructions, and application-specific processor architectures.

 

Practical information

 

This is a collaboration between Inventas, Siemens and InnoFour, combining tools, methodology, and hands-on experience. 

 

 

Details

 

When

Wednesday, October 14, 2026

 

Where 

Inventas AS, Kjølberggata 21, 0653 Oslo Norway

 

Time

09:30 - 17:30 hr