Pre-route Design Flow for Multi-gigabit SerDes Channels
Designing today’s multi-gigabit SerDes channels is challenging. Careful consideration must be given to discontinuities in the channel to ensure reliable and robust product operation. In this webinar, we will show you how to evaluate tradeoffs and derive constraints early in the design cycle, using HyperLynx GHz pre-layout simulation to optimize design critical areas and assess their impact on overall channel performance.
These areas include BGA break-outs, DC blocking capacitors and connector pins, which must be as electrically transparent as possible to maximize channel operating margins.
What You Will Learn
- How to run Channel Operating Margin (COM) analysis on serial channels
- How HyperLynx progressive analysis allows you to isolate and assess the impact of different physical effects on channel margin
- How to create and optimize critical areas using the 3D full-wave solver
- How to use swept parameter analysis to determine which design alternatives provide the best channel margin
Who Should Attend
- Engineering managers
- PCB Design engineers
- Signal Integrity Engineers
- PCB Layout designers
Customer Webinar: Pre-route Design Flow for Multi-gigabit SerDes Channels
Thursday 19th of March 2020
5:00 PM till 6:00 PM CEST