Seminars - Optimizing DDR2/DDR3/LPDDR2 Board Design
Join InnoFour and Mentor Graphics for a seminar on Signal Integrity analysis of DDR2/DDR3/LPDDR2 interface. Learn how advanced simulation technology, packaged within an easy-to-use environment, can dramatically improve your time-to-results, giving you more opportunity to innovate while meeting deadlines and cost goals. In this seminar we will review some of the common challenges you face in your design work such as constraint definition, timing alignment for clock and strobe signals for DDR2/DDR3 designs. We will also look at LPDDR2 interface for low power applications.
Signal Integrity challenges can slow or halt your project schedule. Even if you are working on a good base of theoretical knowledge there are so many variables to make the already complex tasks even more challenging. You will learn new solutions to help you resolve those problems in time and cost efficient ways. We will use cutting edge features of HyperLynx to demonstrate how you can overcome these challenges in your design process. You really can solve very complex design problems in easy-to-use tools with powerful engines beneath the hood.
What You Will Learn
- The differences between DDR, DDR2, and DDR3
- Developing DDR memory subsystem
- Identifying tradeoffs between termination and routing constraints
- Methods for meeting timing and signal integrity requirements
- How decoupling issues can affect your PCB design
- How to analyze your PCB to quickly pinpoint power delivery issues and explore solutions
- How HyperLynx PI can help solidify your PCB power distribution network
About the Presenter: Steve Gascoigne
 | Steve Gascoigne received his EE in Electronics from Exeter University. He has 25 years in the electronics industry, including 14 years as a hardware engineer and PCB designer at Plessey and Nortel networks, and 11 years as a field applications engineer
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Who Should Attend
- Design Engineers
- PCB/Layout Designers
- Signal Integrity Engineers
- DxDesigner, PADS, Expedition, Allegro, and HyperLynx users
Products Covered
Details:
| What: | Seminar Optimizing DDR2/DDR3/LPDDR2 Board Design | ||
| When: | May 10, 2011 | May 11, 2011 | May 12, 2011 |
| Where: | Lund, Sweden | Göteborg, Sweden | Kista, Sweden |
| Time: | 9:30 AM - 3:30 PM | ||
| Registration: | Web | ||
Dive Into Empower 5 With In-Depth Product Training! The Omnify Software User Conference gives you an opportunity to gain in-depth product training, learn best practices, and take your use of Omnify Empower PLM to new levels. Customers who attend the Omnify Software User Conference walk away with a wealth of product knowledge not only for themselves but to share with their colleagues. Even more, the conference is free for customers. The 2011 User Conference will include: • Two full days of Omnify product training • One-on-one, hands-on sessions with Omnify technical staff • More user best practice presentations • More product training sessions • Latest product updates • Focused "shoulmate" networking sessions • Educational take-aways • and much more!
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