Using FPGA I/O Optimizer to Enhance Routability of PCBs that Include FPGAs

Overview

FPGA I/O Optimizer (IOPT) controls, coordinate and optimizes FPGA signal/pin assignments resulting in a significant reduction in design cycle time for PCB designs that include FPGAs. Control is achieved through use of vendor approved parts that thoroughly capture pin functions and bank definitions. Coordination is achieved through import and export of schematic connections, PCB part placement, FPGA vendor pin reports and constraint files, as well as HDL and signal lists. Optimization is achieved through function-aware swapping of pin assignments to potential reduce routing requirements in the PCB. Finally, IOPT provides fast and easy creation of FPGA symbols and their Part definitions.

 

What You Will Learn

• How to implement FPGA I/O Optimizer (IOPT) into an existing PCB design
• How to modify the existing logic symbols to be used with IOPT
• How to reduce the routing requirements by optimizing the netlines between other devices and FPGAs in layout
• How to coordinate pin swapping between the board design and the FPGA design
• A brief overview of the two main flows used with IOPT
• How to simplify the symbol/PDB creation for your FPGA devices

 

Who Should Attend

• Users that have existing designs that would like to implement IOPT to enhance FPGA routing.
• Users that want to understand what IOPT has to offer

 

Details

What

Customer Technical Webcast: Using FPGA I/O Optimizer to Enhance Routability of PCBs that Include FPGAs

 

When
Tuesday the 28th of July 2020

 

Where

Online

 

Time
6:00 PM - 7:00 PM CEST