Verification Workshops

09 November 2016

Verification Workshops

Following on the online seminars about "FPGA Verification Methodology with Formal & Clock Domain Crossing" and "UVM VIP - Evolve your FPGA Verification Methodology" we invite you to attend the free Verification workshops.

In the morning you will learn how to use the push-button formal tools Questa AutoCheck and Questa CDC. You will also learn how to debug and fix bugs and how to use a metastability model created by Questa CDC.


In the afternoon you will learn how to create an UVM environment by using the UVM Framework. You will also learn how to create an UVM environment with the Questa Verification IP configurator. The last lesson is how to reuse both environments in a toplevel environment


You can register for one or both workshops. If you registering for one workshop, please mention this at the remarks section.

Please bring your own laptop to the workshop.


Mark your calendars and sign up for these workshops:

  • 26th of January; Antwerp - Belgium - Register