Web Seminar: PADS Professional FPGA
Speed-up Your PADS FPGA-on-Board Design Flow: Spanning FPGA, Library And Schematic Through To Layout
With the complexity of FPGAs now approaching that of ASICs and SoCs, system designers must consider more advanced FPGA implementation flows. Advanced synthesis technology as part of an integrated FPGA vendor neutral design environment enables architecture-specific optimization that fully utilizes and takes advantage of the specific architectural features for each FPGA device so you meet your design requirements. With this webinar you will learn about FPGA-PCB co-design that integrates synthesis and I/O optimization.
What You Will Learn
- Integration management of cross-domain data and traffic light design flow to manage incremental changes
- Automated, error-free creation of large and complex FPGA Parts/Symbols.
- Using custom FPGA partitioning schemes and assignment of HDL signals to pins while obeying vendor device rules
- How to easily import layouts into the floor planning tool for simultaneous IO Optimization of multiple FPGAs
- Comprehensive device support, including an on-demand service for the very latest devices
Who Should Attend
- FPGA/HDL Designers
- Librarians
- System Designers
- PCB Designers
- Project Managers
About the Presenter: Bas Hassink
Bas Hassink entered EDA in 1999 as a Support Engineer giving support and training in all kinds of applications. His experience lies with PCB Design Systems and Product Lifecycle Management solutions. Bas' aim is to offer customers a professional service and assist in all that InnoFour can provide, whether that is software, training, consultancy, after sales or support.
Details
What
PADS Professional Web Seminar: Speed-up Your PADS FPGA-on-Board Design Flow: Spanning FPGA, Library And Schematic Through To Layout
When
Thursday October 5th, 2017
Where
Online
Time
3:00 PM - 4:00 PM CEST
Sketch routing provides powerful routing automation technology for extraordinary efficiency during PCB layout. High completion rates are accomplished while quality is maintained. Automatically unravel complicated net paths and pin escapes to minimize net lengths and use what-if scenarios to quickly and easily identify the best routing strategies.
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