Calibre Design Solutions

Calibre Physical Verification

The Calibre Physical Verification nmPlatform provides foundries, IDMs, and fabless companies with a comprehensive and innovative suite of functionality that addresses their physical verification needs from established nodes to the most advanced processes.

I want to know more about Calibre Physical Verification
  • Reduces cycle time
  • Reduces iteration and debug time
  • Enables powerful, integrated pattern-based design verification flows

Calibre Physical Verification

The Calibre nmDRC tool has long led the industry, but today’s designs also demand novel technologies that enable design companies to accelerate time to market and achieve faster innovation. From equation-based DRC to multi-patterning, machine learning, and EDA in the cloud, the Calibre toolsuite provides the proven performance, technology, accuracy, and capacity to handle any design, at any node, at any foundry.

Calibre physical verification is the industry leader for accuracy, reliability, and performance. The Calibre nmPlatform provides a comprehensive and innovative suite of functionality that enables foundries, IDMs, and fabless companies to efficiently address all physical verification requirements.

Calibre nmDRC

INDUSTRY-LEADING DRC

Total cycle time is rising due to larger and more complex designs, higher error counts, and more verification iterations.

The Calibre nmDRC platform enables reduced cycle time with revolutionary new capabilities that substantially differentiate Calibre nmDRC design rule checking from traditional DRC tools.

Read Fact Sheet
--

Fields with * are required

Calibre nmDRC Recon

EARLY DESIGN VERIFICATION

The Calibre nmDRC Recon technology reduces iteration and debug time by minimizing the rules and data required for DRC in early design iterations. Results are displayed as color maps to quickly identity root causes of failures, reducing runtime, debug time, and the total number of DRC iteration.

The Calibre nmDRC Recon technology lets design teams perform physical verification of full-chip design layouts during early stages in the design cycle, while different components are still immature.

Read Fact Sheet
--

Fields with * are required

Calibre Pattern Matching

ENABLES COMPLEX CHECKING

At advanced nodes, SoC designers must balance cutomization of SRAM for better performance against potential impacts on yield. Enhancing SRAM debugging with pattern matching and similarity checking enables SRAM designers to find at better, more precise balance between design flexibility and yield.

The Calibre Pattern Matching tool works within the Calibre nmPlatform to enable powerful, integrated pattern-based design verification and manufacturing flows.

Read White Paper
--

Fields with * are required

Calibre Multi-Patterning

COMPREHENSIVE MP TECHNOLOGY 

Calibre Multi-Patterning technology provides industry-leading technology for multi-patterning decomposition, verification, and error debugging. Supports all major foundry methodologies and processes, and provides unique tool integrations and debugging capabilities that ensure a Calibre signoff-quality multi-patterned layout.

View Fact Sheet
--

Fields with * are required

Calibre 3DSTACK

EXTENDS CALIBRE VERIFICATION

Extending physical verification from the IC world to the advanced packaging world to improve multi-die manufacturability. 

Calibre 3DSTACK technology provides comprehensive support for an extensive range of multi-die integration methodologies and processes. Use one Calibre cockpit for assembly-level DRC, LVS and PEX without disruption to traditional packaging formats and tools.

View Fact Sheet
--

Fields with * are required

Calibre Auto-Waivers

AUTOMATED WAIVER MANAGEMENT

The Calibre Auto-Waivers tool provides fast, accurate, automate recognition, removal and tracking of waived design rule violations during DRC. It eliminates costly time and effort from the verification process and also ensures accurate processing of all waiver information on every DRC run.

Calibre Auto-Waivers technology lets users waive false physical and circuit verification violations to focus on real errors, speed design process, make debug more efficient, and shorten schedules.

View Fact Sheet
--

Fields with * are required

READY TO TALK TO SOMEONE TODAY?

We're standing by to answer your questions.

Fields with * are required