Gain a Design-to-revenue Edge in FPGA and SoC Designs with a Full Deployment of Clock-Domain Crossing Analyses and Verification
Overview
Today's complex, multi-clock designs create challenges that must be addressed to avoid costly re-spins and long debug cycles. Design analysis and verification technologies that focus specifically on Clock-Domain Crossing (CDC) issues, using an integrated combination of verification technologies, have become a requirement. Design reviews and stringent methodologies are no longer enough. This web seminar explains the importance of a complete CDC methodology to produce error-free silicon.
What You Will Learn
- The 3 common areas where CDC paths have functional errors
- How Questa CDC products can identify and eliminate all 3 common CDC error types
- Methods for effective CDC verification
Who Should Attend
- ASIC/IC and FPGA Design and Verification Engineers, Project Leads, and Managers
Details
What
Web Seminar: Gain a Design-to-revenue Edge in FPGA and SoC Designs with a Full Deployment of Clock-Domain Crossing Analyses and Verification
When
Thursday the 27th of June 2019
Where
Online
Register
Bijeenkomst: De essentiële rol van (embedded) software in het productontwikkelproces
Performing an Effective Design Review on Power SuppliesThis webinar will address design issues, offer solutions or methods for mitigation in addition to a testing approach to reduce reliability issues to help you improve your best practices.