Evolution of FPGA Verification and How to Address Today's Verification Challenges
Since the advent of digital RTL design in the early nineties, designers have needed to verify their designs. With the increasing complexity of designs, driven by Moore’s law, achieving first pass success has become more challenging. The costs of failure in an ASIC project are obvious (respin NREs above $100k, and months of schedule slip, to name a few). The costs of failure in an FPGA project can be just as detrimental, but aren't as obvious. They include things like missing the market window because of late introduction, or issues with the product in the field (tarnishing your brand).
What You Will Learn
- New technologies with assertions
- Constrained randomization
- Algorithmic test bench design
- Formal verification
Who Should Attend
- Digital ASIC/FPGA designers
- Verification Engineers
- Project Managers
Web Seminar: Evolution of FPGA Verification and How to Address Today's Verification Challenges
Thursday the 22nd of March 2018
Meet us at E-22 electronic fair in Odense this Autumn. We invite you to visit our booth and learn about PADS Professional Premium Edition, Application Lifecycle Management, Xpedition and BOM ConnectorOmnify Empower PLM for Medical Device Manufacturers
This webinar will provide a brief overview and demo of Omnify Empower PLM for Medical Device Manufacturers and is geared towards leads/prospects.