Post-layout Verification of Multi-Gigabit Channels
HyperLynx post-route verification of SerDes channels allows problems to be identified and corrected before the design is fabbed out, greatly reducing debug time in the lab. However, post-route verification requires accurate modeling of the entire multi-gigabit channel and the use of 3D EM solvers to model critical areas of the channel. The process of identifying critical areas, modeling them in 3D and then assembling a model for the full channel can be a complex task, typically reserved for dedicated SI experts. Repeating that task across the dozens or hundreds of serial channels in today’s high-speed design can be especially difficult and time-consuming.
HyperLynx automates this process by using HyperLynx DRC to identify critical areas of the channel, marking a region of the layout that contains the differential signal and its associated return path. These regions are then solved using 3D full-wave electromagnetic simulation, and the resulting models are integrated with transmission line and component models to provide an accurate end-end model of the channel as routed. HyperLynx Compliance analysis quickly determines if the channel meets the requirements for the associated channel protocol and assesses design margin. This automated process can be used to verify designs before fabrication and also to direct optimization efforts if critical areas need to be improved.
In this webinar, we will outline the post-route analysis process, showing you how to perform both post-route verification and optimization. After the webinar, you will be able to download the design and run through the analysis process yourself using step by step instructions.
What You Will Learn
- How to use progressive analysis to verify channel behavior in stages
- How to automatically find and create 3D models for critical areas
- How to validate end to end channels and assess design margin
- How to optimize a critical area using the 3D Explorer
- How to use Channel Operating Margin (COM) analysis to validate all your high speed channels
Who Should Attend
- Engineering Managers
- PCB/System Designers
- Signal Integrity Specialists
- PCB Layout Designers
Customer Webinar: Post-layout Verification of Multi-Gigabit Channels
Thursday the 23rd of April
6:00 PM - 7:00 PM CEST