Workshop: Meeting the Challenges of DDRx Design - Almelo Netherlands

11 May 2010

Workshop: Meeting the design challenges of DDRx Design - Almelo Netherlands

 

Event Type : Workshop

When : 14th of September 2010

Where : Almelo, Netherlands

Time : 09:30 am to 16:30 pm

 

Overview

DDR2 and DDR3 (Double Data Rate) have become the dominant memory standards for high-bandwidth applications, yet developing proper routing constraints and meeting set-up and hold times can be a challenge.

 

In this workshop, we will cover some of the basic electrical requirements of DDR2/DDR3 interfaces, show you how to meet the timing and signal integrity (SI) requirements of these memory interfaces, and provide tips on developing these memory subsystems.

 

Included will be HyperLynx Labs that shows how quickly and easily you can analyze DDRx interfaces for SI and timing issues.

 

What You Will Learn

  • The differences between the DDRx standards
  • Electrical requirements of DDR2 and DDR3
  • How to develop a DDR memory subsystem
  • How to use HyperLynx to validate your DDRx system timing

Who Should Attend

  • Engineers and Managers designing high-speed memory systems
  • Hardware Engineers, Signal Integrity Engineers, and PCB Designers, regardless of EDA tools currently used
  • Current HyperLynx customers interested in DDRx applications (call for special DDRx upgrade pricing!) 

About the Presenter

 

Steve Gascoigne received his EE in Electronics from Exeter University. He has 25 years in the electronics industry, including 14 years as a hardware engineer and PCB designer at Plessey and Nortel networks, and 11 years as a field applications engineer.